An electronic system may comprise software components (e.g., to be executed on a general purpose processor), a general purpose processor (e.g., an Intel® x86 architecture processor), memory (e.g., random access, hard disk or read only) and other hardware components (e.g., field programmable gate arrays (FPGA) or other programmable logic, application specific integrated circuits (ASIC) or a System on Chip (SOC) including software and hardware such as FPGA's or ASIC). The design of such an electronic system may begin with an implementation of selected system functionality in a high-level software programming language (e.g., C, C++, or Pascal). However, depending on design objectives, it may be beneficial to implement selected functions of the system in hardware (e.g., as FPGAs or other programmable logic, ASIC or SOC). However, before incurring the costs associated with physically migrating selected system components to a hardware implementation, designers may choose to model the new hardware implementation (e.g., via emulation or simulation) along with the rest of the system components to ensure that the new system design will function properly once implemented. Furthermore, the new system design, including its hardware and software components, may be modeled together to verify whether system performance may be improved by repartitioning the system between its hardware and software components.
One way to model hardware is to describe system functions to be implemented as hardware in a hardware description language (HDL) (e.g., Verilog, VHDL, SystemC, SpecC, HandeIC, BachC or other suitable hardware description languages) and to use such HDL descriptions in conjunction with electronic design automation (EDA) tools, such as logic simulators (e.g., ModelSim by Mentor Graphics®) and hardware emulators (e.g., an IKOS machine such as VStation by Mentor Graphics®). Once a description of the hardware function is rendered in HDL, the HDL design may be processed to render a gate level design of the hardware using synthesis programs, for instance. Then conventional physical design tools may be used to reduce the gate level design to an actual hardware implementation (e.g., within an FPGA or other programmable logic, ASIC or SOC). Thus, a designer can progress towards an optimized physical implementation of the system design while verifying and evaluating various design options without having to physically implement the various options in actual hardware.
The HDLs however are difficult to learn and require special knowledge. Most ordinary computer programmers are not familiar with such languages. There have been efforts to develop HDLs that are similar in some aspects to conventional software programming languages (e.g., C, C++ or Pascal). For instance, development of System C was one such effort. Even with such improvements, these languages (e.g., SystemC, HandelC, BachC or SpecC) are still HDLs and very different from ordinary high-level software programming languages (e.g., C, C++ or Pascal).
Thus, it may be beneficial to first implement an electronic system design in software using conventional software programming languages (e.g., C, Pascal, or C++) and convert selected system functionality to an HDL description to be modeled as hardware. To this end, EDA tools have been proposed that can take an unmodified high-level programming language description (e.g., C, C++ or Pascal) of an electronic system and convert such a description to an HDL description. For instance, U.S. Pat. No. 6,226,776 to Panchul describes one such system for converting C-type software programs into register transfer level (RTL) HDL descriptions. However, this and other EDA tools and methods for converting system functions described in a conventional software programming language (e.g., C, C++, or Pascal) to an HDL description suffer from many shortcomings that avoid or make difficult the task of converting certain types of software instructions into HDL.
For instance, many of the conventional software programming languages (e.g., C, C++, or Pascal) provide for various instructions to implement memory address dereferencing schemes, such as pointers, arrays and structs. In conventional EDA tools, such memory dereferencing is either not at all converted to HDL or they are done so in an inefficient manner. Thus, there is a need for improved methods and systems for migrating electronic system functions implemented originally using conventional software programming languages (e.g., C, C++, or Pascal) into a hardware representation (e.g., in an HDL such as Verilog, VHDL or System C).